Placement Algorithms and Logic on Logic (lol) 3d Integration
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Authors
Mohammad Trick
- Department of Computer Engineering, Sardasht Branch, Islamic Azad University, Sardasht, Iran.
Behzad Boukani
- Department of Computer Engineering, Sardasht Branch, Islamic Azad University, Sardasht, Iran.
Abstract
In the present study, three algorithms for placement of standard 3D cells have been analyzed. These algorithms are 3D placement using 2D placement devices, real 3D analytic placement using mPL, and 3D placement simultaneously using 2D and mPL placements. These algorithms are used to place three case studies in a real face-to-face 3D process. These three case studies include: two-point FFT butterfly processing element known as PE, advanced embedded series or AES, and wireless decoding with multiple input and multiple output (MIMO). Afterwards, displacements are compared with 2D placements regarding performance and power consumption. Then, using this technology, i.e. face-to-face 3D integration with micro bump along with three placement algorithms, timer speeds of AES and PE modules are respectively increased as 3.15% and 6.22% while their power consumption are reduced to 6.2% and 9.12%, respectively.
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ISRP Style
Mohammad Trick, Behzad Boukani, Placement Algorithms and Logic on Logic (lol) 3d Integration, Journal of Mathematics and Computer Science, 8 (2014), no. 2, 128-136
AMA Style
Trick Mohammad, Boukani Behzad, Placement Algorithms and Logic on Logic (lol) 3d Integration. J Math Comput SCI-JM. (2014); 8(2): 128-136
Chicago/Turabian Style
Trick, Mohammad, Boukani, Behzad. "Placement Algorithms and Logic on Logic (lol) 3d Integration." Journal of Mathematics and Computer Science, 8, no. 2 (2014): 128-136
Keywords
- Placemen
- mPL
- preinvex function
- preinvex function
MSC
References
-
[1]
R. R. Tummala, V. Sundaram, R. Chatterjee, P. M. Raj, N. Kumbhat, V. Sukumaran, V. Sridharan, A. Choudury, Qiao Chen, T. Bandyopadhyay, Trend from ICs to 3D ICs to 3D Systems, Proc. IEEE Conference on Custom Integrated Circuits Conference, (2009), 439-444
-
[2]
H. Yu, Y. Shi, L. He, T. Karnik, Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power, IEEE Transactions on VLSI Systems, 6 (2008), 1609-1619
-
[3]
M. Chan, P. K. Ko, Development of a Viable 3D Integrated Circuit Technology, Science in China, 44 (2001), 241-248
-
[4]
T. Mitsuhashi, et al., Development of 3-D-packaging process technology for stacked memory chips, In Proc. IEEE International 3D Systems Integration Conference, (2006), 155–162
-
[5]
Y. Xie, J. Cong, S. Sapatnekar, Eds., Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures, Springer Publishers, (2009)
-
[6]
B. Goplen, S. S. Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach, in Proc. of the Int. Conf. on Comput.- Aided Des., (2003), 86 - 89
-
[7]
R. Patti, Three-dimensional integrated circuits and the future of systemon- chip designs, Proceedings of the IEEE, 94 (2006), 1214–1224
-
[8]
B. S. Feero, P. P. Pande, Networks-on-chip in a threedimensional environment: A performance evaluation, IEEE Transactions on Computers, 58(1) (2009), 32–45
-
[9]
Tezzaron, Wafer stack with super-contacts, [Online].Available: http://www.tezzaron.com/about/PhotoAlbum/Products/Wafer Pair Super -Contacts.html., ()
-
[10]
K. Puttaswamy, G. H. Loh, 3D-integrated SRAM components for high-performance microprocessors, IEEE Transactions on Computers, 58(10) (2009), 1369–1381
-
[11]
J. Cong, G. Luo, A multilevel analytical placement for 3d ics, in ASP-DAC ’09: Proceedings of the 2009 Asia and South Pacific DesignAutomation Conference. Piscataway, NJ, USA: IEEE Press, (2009), 361–366.
-
[12]
R. Enbody, G. Kwee, H. Tan, Routing the 3-d chip, in Proceedings of the 1991 Design Automation Conference, (1991), 132 –137.
-
[13]
C. C. Tong, C.-L. Wu, Routing in a three-dimensional chip, Computers, IEEE Transactions on, 44 (1995), 106 –117
-
[14]
T. Thorolfsson, N. Moezzi-Madani, P. D. Franzon, Reconfigurable five layer 3d integrated memory-on-logic synthetic aperture radar processor, To appear in Computers Digital Techniques, IET, vol. 4, no. 6 (2010)
-
[15]
C. Lee, An algorithm for path connections and its applications, IRE Transactions on Electronic Computers, 10 (1961), 346–365